The present invention relates to a power and signal connection system for a dense integrated circuit multi-chip package and to a fluid cooling system for the package.
In the design of high speed digital computers, the aim is to fit the largest number of silicon integrated circuit (IC) packages or chips into the least volume. The methods evolved for housing, interconnecting and cooling such chips have an important bearing on the performance and reliability of the computer.
Improvements in the design and fabrication of microelectronic devices have greatly increased the number of logic functions and data storage that can be put on a chip. There is also a tendency for the chips size to increase to the point where very large numbers of closely spaced terminals, in the range of 250-400, must be connected.
The combination of high interconnect density, high power and high computational speed requirements pose severe problems for chip packaging design technology. For example, the control of electrical parameters, such as impedance, which affect the characteristics of the transmission lines interconnecting the chips within the package, is of extreme importance if high speeds are to be attained. It is also important to maintain the correct working environment for the chips by providing a properly engineered heat transfer system. Furthermore, the chips should be free of mechanical stress during the process steps of fabricating the package and also during the subsequent operation of the package. These and other design considerations and problems are discussed more fully below as a preface to the description of the related solutions which are provided by the high density multi-chip package of the present invention.
In general, the characteristics of the transmission lines which interconnect chips within a package are affected by the direct current resistance of the lines and by the other impedance of the lines. The impedance of a line is a function of inductance, capacitance and resistance. These in turn depend upon the geometry of the line and the electrical and magnetic properties of the line and of its environment. High impedance values cause signal attenuation. In addition, mismatches between the impedance and the load resistance cause signal reflections. Discontinuities in the transmission lines associated with the routing of the line are a primary cause of this impedance mismatch. Such discontinuities also contribute to propagation delays and to unequal propagation times along different transmission line paths.
In terms of the minimum feature size and device density, the scale of integration of semiconductor devices on integrated circuit chips has improved greatly since the middle and late 1970's. Device densities have progressed from large scale integration (LSI) to very large scale integration (VLSI) and toward ultra-large scale integration (ULSI). As device densities have increased and as high density multi-chip packaging has been developed, both logic capabilities and data storage capacities have increased. In addition, the increased densities have decreased the transmission line path lengths somewhat. This has decreased the transmission times, for both device-to-device and chip-to-chip communications. Nonetheless, device switching speeds have also decreased, to the single nanosecond level. As a consequence, transmission times have become the primary component in propagation delays. That is, the path length of signal lines is the primary factor limiting the speed of operation of high speed computers. Thus, one crucial industry need is to further decrease the transmission line path lengths and, at the same time, to increase the uniformity of the electrical and magnetic characteristics of such lines in order to provide uniform, controlled signal transmission characteristics.
In addition to the sensitivity to uniform transmission characteristics and to the need for increasingly short transmission times, the increased size and density of VLSI and ULSI chips and the high density packaging require an increased number and density of contacts. Increasing the number of densely spaced contacts causes routing problems, and, ultimately, problems in achieving uniform, controlled signal transmission line characteristics. In addition, the increased on-chip device densities and increased chip-to-chip densities are accompanied by a large increase in power consumption per unit area and by problems in removing the resulting heat from the package.
Convective air cooling is thought to have been the prevalent prior art heat removal technique. However, as applied to high density logic, multi-chip, main frame computers, the high time volume of air required for convection air cooling necessitates blowers and large ducts. Such structural features use space that could otherwise be allocated to integrated circuits, and generate high noise levels.
An alternative approach, which increases the effectiveness of convection air cooling, is intermediate air cooling. In this technique, the heat is dissipated from the multi-chip micro-package by convection cooling using air that is pre-cooled by an external heat exchanger. The basic problem with this technique, however, is condensation by the chilled air, which can cause corrosion and which requires stringent air quality control.
An alternative to air cooling and pre-chilled or intermediate air cooling is to liquid cool the chip micropackages. One such technique, termed silent liquid integral cooling (SLIC) is disclosed in Wilson, "Cooling Modern Main Frames-A Liquid Approach" Computer Design, May, 1983, pp 219-225. Basically, the cooled liquid is applied "directly" to the back of the micro-package via a conformal intermediate copper sheet.
Another liquid cooling approach for multi-chip micro-packages involves the use of spring-loaded aluminum piston heat sinks mounted in an array corresponding to the chips. This technique is described, for example, in Blodgett et al, "Thermal Conduction Module: A High-Performance Multi-Layer Ceramic Package", IBM J. Res. 1 Develop. 26, 1, January, 1982, pp 30-35. See also Blodgett, "Microelectronic Packaging", Scientific American, pp 86-96. Referring to FIG. 1, using this approach an integrated circuit 10 is connected by solder ball-bonded contacts 11 to a multi-layer ceramic substrate 12 that contains all the chip interconnections and the pins 13 for connecting the chip signal and voltage contacts to an associated mother board. The spring-loaded pistons 14 are mounted within hat 16, which is cooled by a water-cooled cold plate 17. The individual piston heat sinks 14 contact associated individual chips via the rounded, ball-type bottom surface 18 of the heat sink. This ensures controlled-pressure contact between the heat sink and the associated integrated circuit chip. This structure provides essentially point contact whereas large area contact is necessary for uniform high thermal flux density, that is, for effective heat transfer. In addition, the cold plate 17 and the coolant flow therein are spaced some considerable distance from the heat transfer interface, which increases the resistance of the internal heat flow path.
Still another approach for cooling a leadless chip carrier is depicted in FIG. 2. In this system, leadless chip carriers 20 are mounted between a pair of heat sink pillars 21 and 22. The chip carriers 20 are interconnected by solder pillars 23 which bond the peripheral chip contacts to printed wiring board interconnect circuits 24. The chip is supported at the bottom by the heat sink pillar 21 and at the top by a spring heat sink 26 which is mounted within the upper heat sink pillar 22. The pillars are held together by screw 27. This arrangement apparently provides good conformal heat sink contact at both surfaces of the chip carrier. However, its heat dissipation efficiency is diminished since the heat transer surface is not contacted by the full surface area of the chip and the cold plate geometry has limited heat transfer efficiency with the cooling fluid. Further, intimate contact between the chip and the cold plate surface depends upon the ability of the printed wiring board to deform to accommodate dimensional tolerance inaccuracies. This interacts adversely with the system of pressure springs.
Still another consideration in the design and cooling of multi-chip integrated circuit packages is the thermal coefficient of expansion (TCE) of the various materials used in the assembly. Thermal-induced stress is an especially difficult problem for solder joints and other types of metallurgically-bonded joints, such as, for example, the joints between the chip contact pads of leadless chip carriers and the contact pads of substrate interconnect assemblies. TCE-induced stresses can result from the use of different materials in the conductors which meet at the joint. TCE stress also results from the overall different thermal expansion characteristics of the chip carrier and the substrate. The TCE mismatch between the chip carrier and substrate is a potentially catastrophic problem, both during the oven cycling which is used for military specifications and, more significantly for commercial applications, during the usual power cycling. The problem of solder joint damage due to flexure and, in particular, the problem of TCE differences between chip carriers and substrates, are discussed, for example, in Markstein, "Surface-Mount Substrates-The Key in Going Leadless", Electronic Packaging and Production, June, 1983, pp 50-55.
Of the conventional approaches available for alleviating the TCE mismatch (expansion restraints, compliant layers and compliant leads), the compliant lead approach using leads formed of stress-compliant materials is presently thought to be the most effective. However, while some of the thermal stress relief techniques may be relatively effective in alleviating stress during heating, virtually all are ineffective in combating thermal-induced stress during cooling cycles.
Finally, but not exhaustively, another problem for closely spaced conductors is cross-talk, which is associated with mutual inductive and capacitive coupling. To alleviate cross-talk, multi-layer chip interconnect assemblies should be formable with the transmission lines encased in an insulator sandwiched between two voltage reference planes. This structure also contributes to uniform well-defined impedance in the transmission lines.